1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to an integrated circuit with a signal bus formed by cell abutment of logic cells.
2. Description of Related Art
Many designs for integrated circuits use standard cell libraries. The standard cell libraries provide the building blocks of logic cells to allow designers to go quickly from circuit design to semiconductor chip fabrication and test. Metal interconnects are employed to connect signals to each of the logic cells in an integrated circuit.
One example using metal interconnects to distribute a signal to logic cells is a sleep signal for sleep transistors. Sleep transistors have been added to the functionality of logic cells available in standard cell libraries. The sleep transistors are controlled by the sleep signal and provide the ability to control power consumption in the individual logic cells.
A sleep signal may be used by sleep transistors to switch the individual logic cells into sleep mode. In sleep mode, the power consumption of the individual logic cells is reduced. Sleep transistors may be particularly important in devices using integrated circuits in which lower power consumption is an important feature as, for example, in cell phones or mobile computers.
Because space in an integrated circuit is limited, the space occupied by the sleep transistors and related circuitry needs to be minimized. The addition of the sleep transistors to standard cells has caused the height of the logic cell to increase. The added sleep transistors also require additional routing resources, which are limited due to the preexisting design of the integrated circuit layout. A separate sleep pin is also required to receive the sleep signal in each individual logic cell with a sleep transistor. Thus, the addition of sleep transistors to standard cells has resulted in increased complexity that may result in layout congestion and blockages.
FIG. 1 is an illustration of integrated circuit layout 100 employing sleep circuitry in the prior art. Integrated circuit layout 100 includes four logic cells 111, 112, 113 and 114. Integrated circuit layout 100 also includes VDD power bus 120, VDD tap 125, VSS power bus 130, VSS tap 135, sleep pin 140, sleep transistor 150, and gate 160. Integrated circuit layout 100 has height 180.
Logic cell 111 draws its power from VDD power bus 120, and from VSS power bus 130 as controlled by sleep transistor 150. Logic cell 111 comprises sleep transistor 150 and gate 160 coupled to sleep pin 140. Sleep transistor 150 may be configured to switch VSS power to the logic cell 111 on and off in response to a sleep signal received at sleep pin 140, and thereby to control power consumption in logic cell 111.
Each logic cell 111, 112, 113, and 114 contains sleep circuitry comprising a sleep transistor substantially similar to sleep transistor 150. Sleep pin 140 requires a metal layer and a second metal interconnect drop using a via to connect the sleep pins from each logic cell 111, 112, 113, and 114, thus requiring two routing resources, the metal layer and the metal interconnect. In addition, logic cells may be defined in increments of tracks, such that when routing metal interconnects the number of tracks is a whole number. In FIG. 1, the addition of sleep circuitry requires an additional track for routing the metal interconnect, resulting in an increase in height 180 and area of the logic cells 111, 112, 113, and 114 by approximately 11%.
In another example, Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) integrated circuits use one or more sleep transistors located in one region of an integrated circuit. A virtual ground from a plurality of logic cells is routed to the drains of the sleep transistors, thus controlling the power for the plurality of logic cells. MTCMOS suffers, however, from the phenomena of electro-migration. Since the virtual ground carries a pulsed direct current, electro-migration limits the long-term reliability of the integrated circuit. In addition, the use of virtual ground typically requires another track of height in the cell.
Thus, adding sleep circuitry comprising sleep transistors to the individual logic cells in the standard cell libraries has several disadvantages. The disadvantages include increasing the height of the logic cells, the addition of a metal layer, the congestion and resulting difficulty of routing to the sleep pin in each logic cell, and the problem of electro-migration in the MTCMOS example.